Document Outline

• 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Contents
• About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
  • 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
  • 40-100GbE IP Core Device Family and Speed Grade Support
    • Device Family Support
    • 40-100GbE IP Core Device Speed Grade Support
  • IP Core Verification
    • Simulation Environment
    • Hardware Testing
  • Performance and Resource Utilization
    • Resource Utilization for 40GbE IP Cores
    • Resource Utilization for 100GbE IP Cores
      • Resource Utilization for 100GbE CAUI–4 IP Cores
  • Release Information
• Getting Started
  • Installing and Licensing IP Cores
    • OpenCore Plus IP Evaluation
  • Specifying the 40-100GbE IP Core Parameters and Options
  • IP Core Parameters
  • Files Generated for the 40-100GbE IP Core
  • Simulating the IP Core
  • Integrating Your IP Core in Your Design
    • Pin Assignments
    • External Transceiver Reconfiguration Controller
    • Placement Settings for the 40-100GbE IP Core
  • 40-100GbE IP Core Testbenches
    • Testbenches with Adapters
    • Testbenches without Adapters
    • Understanding the Testbench Behavior
  • Simulating the 40‑100GbE IP Core With the Testbenches
    • Generating the 40-100GbE Testbench
    • Simulating with the Modelsim Simulator
    • Simulating with the NCSim Simulator
    • Simulating with the VCS Simulator
    • Testbench Output Example: 40GbE IP Core with Adapters
    • Testbench Output Example: 100GbE IP Core with Adapters
  • Compiling the Full Design and Programming the FPGA
  • Initializing the IP Core
• Functional Description
  • High Level System Overview
  • 40-100GbE MAC and PHY Functional Description
    • 40-100GbE IP Core TX Datapath
      • Preamble, Start, and SFD Insertion
      • Address Insertion
      • Length/Type Field Processing
      • Frame Padding
      • Frame Check Sequence (CRC-32) Insertion
      • Inter‑Packet Gap Generation and Insertion
    • 40-100GbE IP Core TX Data Bus Interfaces
      • 40-100GbE IP Core User Interface Data Bus
      • 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
      • 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
      • Bus Quantization Effects With Adapters
      • User Interface to Ethernet Transmission
        • 40GbE IP Core Without Adapters
        • 100GbE IP Core Without Adapters
        • Order of Transmission
    • 40-100GbE IP Core RX Datapath
      • 40-100GbE IP Core RX Filtering
      • 40-100GbE IP Core Preamble Processing
      • 40-100GbE IP Core FCS (CRC-32) Removal
      • 40-100GbE IP Core CRC Checking
      • RX CRC Forwarding
      • RX Automatic Pad Removal Control
      • Address Checking
      • Inter‑Packet Gap
      • Pause Ignore
    • 40-100GbE IP Core RX Data Bus Interfaces
      • 40-100GbE IP Core User Interface Data Bus
      • 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)
      • 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
      • 100GbE IP Core RX Client Interface Examples
      • Error Conditions on the RX Datapath
    • 40GbE Lower Rate 24.24 Gbps MAC and PHY
    • 100GbE CAUI–4 PHY
    • External Reconfiguration Controller
    • Congestion and Flow Control Using Pause Frames
      • Conditions Triggering XOFF Frame Transmission
      • Conditions Triggering XON Frame Transmission
      • Pause Transmission Logic
    • Pause Control and Generation Interface
    • Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
    • 40-100GbE IP Core Modes of Operation
    • Link Fault Signaling Interface
    • Statistics Counters Interface
    • MAC – PHY XLGMII or CGMII Interface
      • MAC to PHY Connection Interface
    • Lane to Lane Deskew Interface
    • PCS Test Pattern Generation and Test Pattern Check
    • Transceiver PHY Serial Data Interface
      • PCS BER Monitor
    • 40GBASE-KR4 IP Core Variations
      • 40GBASE-KR4 Reconfiguration Interface
      • 40GBASE-KR4 Microprocessor Interface
    • Control and Status Interface
    • Clocks
    • Resets
  • Signals
    • Signals of MAC and PHY Variations Without Adapters
    • Signals of MAC and PHY Variations With Adapters
    • Signals of 40-100GbE MAC‑Only IP Core Variations
    • Signals of 40-100GbE PHY‑Only IP Core Variations
  • Software Interface: Registers
    • 40-100GbE IP Core Registers
      • Transceiver PHY Control and Status Registers
      • Lock Status Registers
      • Bit Error Flag Registers
      • PCS Hardware Error Register
      • BER Monitor Register
      • Test Mode Register
      • Test Pattern Counter Register
      • Link Fault Signaling Registers
      • MAC and PHY Reset Registers
      • PCS‑VLANE Registers
      • PRBS Registers
      • 40GBASE-KR4 Registers
      • MAC Configuration and Filter Registers
      • Pause Registers
      • MAC Hardware Error Register
      • CRC Configuration Register
      • MAC Feature Configuration Registers
      • MAC Address Registers
      • Statistics Registers
    • 40‑100GbE Example Design Registers
      • PMD Registers
      • MDIO Registers
      • 2‑Wire Serial Interface Registers
  • Ethernet Glossary
• Debugging the 40GbE and 100GbE Link
• 40-100GbE IP Core Example Design
• Address Map Changes for the 40-100GbE IP Core v12.0 Release
• 10GBASE-KR Registers
  • 10GBASE-KR PHY Register Definitions
• Additional Information
  • 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History
  • How to Contact Altera
  • Typographic Conventions