Nortel Networks Circuit Card - Manual (Page 788)

Page 788 of 906 NTBK51 Downloadable D-channel Handler daughterboard
553-3001-211 Standard 3.00 August 2005
Main memory
The main 68EC020 system memory is comprised of 1 Mbyte of SRAM and
is accessible in 8 or 16 bits. The software, base code and application reside in
main RAM and is downloaded from the software through the shared memory.
Shared memory
The shared memory is the interface between the CPU and the 68EC020 MPU.
This memory is a 16 Kbyte RAM, expandable to 64 kbytes and accessible in
8 or 16 bits.
EPROM memory
The Bootstrap code resides in this 27C1000 EPROM and is executed on
power up or reset.
Flash EPROM memory
Flash EPROM provides non-volatile storage for the DDCH loadware which
minimizes the impact to sysload. The Flash EPROM provides an increase in
system service with a reduced delay after a brown-out, and faster testing of a
hardware pack after it is plugged in.
EEPROM memory
The DDCH uses a 1024 bit serial EEPROM for storing the Nortel product
code and a revision level. This information can be queried by the software.
Serial communication controller
The serial controller is the Zilog Z16C35 and is referenced as the Integrated
Controller (ISCC). The ISCC includes a flexible Bus Interface Unit (BIU)
and four Direct Memory Access (DMA) channels, one for each receive and
transmit. The DMA core of the ISCC controls the data transfer between local
RAM and the communication ports.