Altera Quartus II Settings File - Manual (Page 109)

IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
Instructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilog
and VHDL design files. You can use this option to disable these synthesis directives and include
previously ignored code during elaboration.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <value>
Default Value
Off
Example
set_global_assignment -name ignore_translate_off_and_synthesis_off on
MNL-Q21005
2015.05.04
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 109
Quartus Settings File Reference Manual Altera Corporation
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