Altera Quartus II Settings File - Manual (Page 692)

PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
Allows the Fitter to set the phase shift of a PLL output counter, and hence the phase shift of its generated
clock, to improve timing for all edges affected by this clock. Apply multicycle timing exceptions to paths
between the generated clock and other clocks in the design to avoid timing violations.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to <to> -
entity <entity name> <value>
692 PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
Send Feedback