Altera Quartus II Settings File - Manual (Page 186)

USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
Directs the compiler to use LogicLock constraints during DSP and RAM balancing.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING <value>
Default Value
On
Example
set_global_assignment -name use_logiclock_constraints_in_balancing on
186 USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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