Lvds_fixed_clock_data_phase – Altera Quartus II Settings File User Manual
Page 261
LVDS_FIXED_CLOCK_DATA_PHASE
Specifies exact skew compensation. When the fixed clock-to-data skew is known, clock data
synchronization (CDS) can be pre-programmed into the device during configuration. If CDS is pre-
programmed into the device, training patterns do not need to be transmitted to the receiver channels. The
resolution of each pre-programmed setting is 25% of the data period, to compensate for skew up to 50%
of the data period. This option is applied only to input pins that drive the rx_in[] port of the altlvds_rx
megafunction. This option is available for APEX II devices only.
Type
Enumeration
Values
• Default
• Negative 180
• Negative 90
• Positive 180
• Positive 90
• Zero
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_instance_assignment -name LVDS_FIXED_CLOCK_DATA_PHASE -to <to> -entity
<entity name> <value>
MNL-Q21005
2015.05.04
LVDS_FIXED_CLOCK_DATA_PHASE
261
Quartus Settings File Reference Manual
Altera Corporation