Altera Quartus II Settings File - Manual (Page 685)

PLL_COMPENSATE
Allows you to specify an output pin as a compensation target for a PLL in ZERO_DELAY_BUFFER or
EXTERNAL_FEEDBACK mode, or an input pin or a group of input pins as compensation targets for a
PLL in SOURCE_SYNCHRONOUS mode. If assigned to an output pin, the pin must be fed by the
external clock output port of a PLL in a Stratix, Hardcopy Stratix or Cyclone device, or the compensated
clock output port of a PLL in other devices. Any other output pins fed by the same PLL generally are not
delay compensated, especially if they have different I/O standards. If assigned to an input pin or a group
of input pins, the input pins must drive input registers that are clocked by the compensated clock output
port of a PLL in SOURCE_SYNCHRONOUS mode. This option is ignored if it is applied to anything
other than an output or input pin as described previously.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name PLL_COMPENSATE -to <to> -entity <entity name>
<value>
MNL-Q21005
2015.05.04
PLL_COMPENSATE 685
Quartus Settings File Reference Manual Altera Corporation
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