Altera Quartus II Settings File - Manual (Page 89)

EXTRACT_VERILOG_STATE_MACHINES
Allows the Compiler to extract state machines from Verilog Design Files. The Compiler optimizes state
machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler
extracts and optimizes state machines in Verilog Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES <value>
Default Value
On
Example
set_global_assignment -name extract_verilog_state_machines off
See Also
State Machine Processing Extract VHDL State Machines
MNL-Q21005
2015.05.04
EXTRACT_VERILOG_STATE_MACHINES 89
Quartus Settings File Reference Manual Altera Corporation
Send Feedback