Altera Quartus II Settings File - Manual (Page 180)

SYNTH_TIMING_DRIVEN_SYNTHESIS
Allows synthesis to use timing information during synthesis to better optimize the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS <value>
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -entity <entity
name> <value>
set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -to <to> -
entity <entity name> <value>
Example
set_global_assignment -name synth_timing_driven_synthesis on
180 SYNTH_TIMING_DRIVEN_SYNTHESIS
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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