Altera Quartus II Settings File - Manual (Page 159)

SAFE_STATE_MACHINE
Tells the compiler to implement state machines that can recover gracefully from an illegal state.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SAFE_STATE_MACHINE -entity <entity name> <value>
set_instance_assignment -name SAFE_STATE_MACHINE -to <to> -entity <entity
name> <value>
set_global_assignment -name SAFE_STATE_MACHINE <value>
Default Value
Off
Example
set_global_assignment -name safe_state_machine on
set_instance_assignment -name safe_state_machine on -to foo
See Also
State Machine Processing Extract Verilog State Machines Extract VHDL State Machines
MNL-Q21005
2015.05.04
SAFE_STATE_MACHINE 159
Quartus Settings File Reference Manual Altera Corporation
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