Altera Quartus II Settings File - Manual (Page 374)

EDA_RTL_TEST_BENCH_FILE_NAME
Specifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL Test
Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), or Verilog HDL file (.v).
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id
<section identifier> <value>
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity
name> -section_id <section identifier> <value>
374 EDA_RTL_TEST_BENCH_FILE_NAME
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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