Altera Quartus II Settings File - Manual (Page 152)

REMOVE_REDUNDANT_LOGIC_CELLS
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a
circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <entity
name> <value>
set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to <to> -entity
<entity name> <value>
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <value>
Default Value
Off
Example
set_global_assignment -name remove_redundant_logic_cells on
set_instance_assignment -name remove_redundant_logic_cells on -to node
152 REMOVE_REDUNDANT_LOGIC_CELLS
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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