Altera Quartus II Settings File - Manual (Page 354)

EDA_GENERATE_FUNCTIONAL_NETLIST
Generate Verilog or VHDL netlist for functional simulation with EDA simulation tools. The SDF Timing
file (.sdo) is not generated for the project. This option is not available for the VCS MX simulation tool.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id
<section identifier> <value>
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity <entity
name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
354 EDA_GENERATE_FUNCTIONAL_NETLIST
MNL-Q21005
2015.05.04
Altera Corporation Quartus Settings File Reference Manual
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