Altera Quartus II Settings File - Manual (Page 29)

Analysis & Synthesis Assignments
ADV_NETLIST_OPT_ALLOWED
Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level
retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the
Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming
during netlist optimization, only if doing so does not negatively affect the timing or performance of the
design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so
affects the timing or performance of the design. Altera does not recommend using this setting. If this
option is set to 'Never Allow' the Compiler cannot alter the node or entity.
Type
Enumeration
Values
• Always Allow
• Default
• Never Allow
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name>
<value>
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity
<entity name> <value>
Example
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg
MNL-Q21005
2015.05.04
Analysis & Synthesis Assignments 29
Quartus Settings File Reference Manual Altera Corporation
Send Feedback