Physical_synthesis_asynchronous_signal_pipelining – Altera Quartus II Settings File User Manual
Page 673
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
Specifies that Quartus II should perform automatic insertion of pipeline stages for asynchronous clear and
asynchronous load signals during fitting to increase circuit performance. This option is useful for
asynchronous signals that are failing recovery and removal timing because they feed registers using a
high-speed clock.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRO-
NOUS_SIGNAL_PIPELINING <value>
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRO-
NOUS_SIGNAL_PIPELINING -entity <entity name> <value>
set_instance_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRO-
NOUS_SIGNAL_PIPELINING -to <to> -entity <entity name> <value>
Default Value
Off
MNL-Q21005
2015.05.04
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
673
Quartus Settings File Reference Manual
Altera Corporation