Altera Quartus II Settings File - Manual (Page 283)

ACLK_RULE_SZER_BTW_ACLK_DOMAIN
Direct Design Assistant to detect synchronizer for every signal between asynchronous clock domains on
the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN <value>
MNL-Q21005
2015.05.04
ACLK_RULE_SZER_BTW_ACLK_DOMAIN 283
Quartus Settings File Reference Manual Altera Corporation
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