Altera Quartus II Settings File - Manual (Page 191)

VERILOG_NON_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that do not evaluate to compile-time
constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they
exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT <value>
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity <entity
name> <value>
set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to <to> -
entity <entity name> <value>
Default Value
250
Example
set_global_assignment -name verilog_non_constant_loop_limit 3000
MNL-Q21005
2015.05.04
VERILOG_NON_CONSTANT_LOOP_LIMIT 191
Quartus Settings File Reference Manual Altera Corporation
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