Motorola MC68VZ328 - Manual (Page 112)

7-2 MC68VZ328 User’s Manual
Introduction to the DRAM Controller
Figure 7-1. DRAM Controller Block Diagram
Data
SYSCLK
Control
Address
CLK32
CSD0
CSD1
MD[15:0]
MP
U I
n
te
rfac
e
Mode
Refresh
DRAM
DRAM Address
Control
DTACK
RAS0
A[31:1]
RAS1
CAS0
CAS1
Control
Control
Control
Signal
Control
Page Access
(from LCD)
8-Bit Port
(from SIM)