Motorola MC68VZ328 - Manual (Page 143)

Programming Model
LCD Controller 8-15
LBLKC LCD Blink Control Register 0x(FF)FFFA1F
8.3.9 LCD Panel Interface Configuration Register
The LCD panel interface configuration (LPICF) register is used to determine the data bus width of the
LCD panel and to determine if it is a black-and-white or grayscale display. The bit assignments for the
register are shown in the following register display. The settings for the bits in the register are listed in
Table 8-10.
LPICF LCD Panel Interface Configuration Register 0x(FF)FFFA20
BIT 7 6 5 4 3 2 1 BIT 0
BKEN BD6 BD5 BD4 BD3 BD2 BD1 BD0
TYPE rw rw rw rw rw rw rw rw
RESET
0 1 1 1 1 1 1 1
0x7F
Table 8-9. LCD Blink Control Register Description
Name Description Setting
BKEN
Bit 7 Blink Enable—This bit determines if the cursor will blink or remain
steady. 1 = Blink is enabled
0 = Blink is disabled (default)
BDx
Bits 6–0 Blink Divisor 6–0—These bits determine if the cursor will toggle
once per a specified number of internal frame pulses plus one. The
half-period may be as long as 2 seconds. See description
BIT 7 6 5 4 3 2 1 BIT 0
PBSIZ1–0 GS1–0
TYPE rw rw rw rw
RESET
0 0 0 0 0 0 0 0
0x00
Table 8-10. LCD Panel Interface Configuration Register Description
Name Description Setting
Reserved
Bits 7–4 Reserved These bits are reserved and should be set to 0.
PBSIZ1–0
Bits 3–2 Panel Bus Width 1–0—These bits specify
the bus width of the LCD panel. 00 = 1 bit.
01 = 2 bit.
10 = 4 bit.
11 = 8 bit.
GS1–0
Bits 1–0 Grayscale Mode Selection 1–0—These
bits determine the mode of operation of the
grayscale display device. 00 = Black-and-white mode.
01 = Four-level grayscale mode.
10 = Sixteen-level grayscale mode.
11 = Reserved.