Motorola MC68VZ328 User Manual

Page 167

Advertising
background image

Programming Model

Interrupt Controller

9-17

IRQ5
Bit 20

Interrupt Request Level 5—This bit, when set, indicates that an
external device is requesting an interrupt on level 5. If the IRQ5 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared.

0 = No level 5 interrupt is

pending.

1 = A level 5 interrupt is

pending.

IRQ6
Bit 19

Interrupt Request Level 6—This bit, when set, indicates that an
external device is requesting an interrupt on level 6. If the IRQ6 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ6 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.

0 = No level 6 interrupt is

pending.

1 = A level 6 interrupt is

pending.

IRQ3
Bit 18

Interrupt Request Level 3—This bit, when set, indicates that an
external device is requesting an interrupt on level 3. If the IRQ3 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ3 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.

0 = No level 3 interrupt is

pending.

1 = A level 3 interrupt is

pending.

IRQ2
Bit 17

Interrupt Request Level 2—This bit, when set, indicates that an
external device is requesting an interrupt on level 2. If the IRQ2 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ2 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.

0 = No level 2 interrupt is

pending.

1 = A level 2 interrupt is

pending.

IRQ1
Bit 16

Interrupt Request Level 1—This bit, when set, indicates that an
external device is requesting an interrupt on level 1. If the IRQ1 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ1 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.

0 = No level 1 interrupt is

pending.

1 = A level 1 interrupt is

pending.

Reserved
Bits 15–14

Reserved

These bits are reserved and
should be set to 0.

PWM2
Bit 13

Pulse-Width Modulator 2 Interrupt—This bit indicates an interrupt
event from PWM unit 2 is pending. The interrupt level is configurable
from level 1 to level 6. See Section 9.6.6, “Interrupt Level Register,”
for more details.

0 = No PWM 2 interrupt.
1 = A PWM 2 interrupt is

pending.

UART2
Bit 12

UART 2 Interrupt Request—When this bit is set, it indicates that the
UART 2 module needs service. The interrupt level is configurable
from level 1 to level 6. See Section 9.6.6, “Interrupt Level Register,”
for more details.

0 = No UART 2 interrupt

request is pending.

1 = UART 2 interrupt request

is pending.

INT3
Bit 11

External INT3 Interrupt—This bit, when set, indicates that a level 4
interrupt has occurred. It is usually for a keyboard interface. When it
is programmed as edge-triggered, it can only be cleared by writing a
1 to the port D register. See Section 10.4.5, “Port D Registers,” on
page 10-16
for details.

0 = No INT3 interrupt is

pending.

1 = An INT3 interrupt is

pending.

Table 9-7. Interrupt Pending Register Description (Continued)

Name

Description

Settings

Advertising