Motorola MC68VZ328 - Manual (Page 117)

DRAM Controller Operation
DRAM Controller 7-7
7.2.2 DTACK Generation
In a 16 MHz system frequency, 60 ns DRAM can support a zero wait state (4 clocks per access) for CPU
bus cycles. Therefore, DTACK
is only delayed for refresh operations that occur before a read/write access
cycle. The value of N clocks (N is the number of system clock cycles required for refresh) will be inserted
into a read or write cycle when the CPU cycle collides with a refresh cycle. Refresh, in this case, has a
higher priority.
NOTE:
The value of N can be 1–4 clocks, depending on the collision overlap of
the refresh cycle and CPU bus cycle.
7.2.3 Refresh Control
During normal operation, the MC68VZ328 DRAM cycles are distributed evenly over the refresh period.
The DRAM refresh rate requirement may vary between different DRAM chips. Users can program the
REF field in the DRAM configuration register (DRAMMC) to select the required refresh frequency.
The following examples demonstrate refresh values using two different settings and clock sources:
• When CLK32 = 32.768 kHz:
— CLK = 0
— DRAMMC register value (REF) = 0
— refresh period = 15.2
µ
s
• If SYSCLK = 16.58 MHz:
— CLK = 1
— DRAMMC register value (REF) = 7
— refresh period = 15.44
µ
s