Motorola MC68VZ328 - Manual (Page 131)

LCD Controller Operation
LCD Controller 8-3
The LCD interface logic is used to pack the display data into the correct size and output it to the LCD
panel’s data bus. The polarity of the LFLM, LP, and LCLK
signals and pixel data can all be programmed
to suit different LCD panel requirements.
8.2.1 Connecting the LCD Controller to an LCD Panel
The following signals are used to connect the LCD controller to an LCD panel:
• LD[7:0]—The LCD Data bus lines transfer pixel data to the LCD panel so that it can be displayed.
Data is arranged differently on the bus, depending on which LCD panel mode is selected. The
output pixel data can be negated through programming. See Section 8.3.10, “LCD Polarity
Configuration Register,” for more information. The LCD controller is initially configured to drive
single-screen monochrome LCD panels. The data bus size for an LCD panel can be configured to
1, 2, 4, or 8 bits by programming the LPICF register.
• LFLM—The LCD Frame Marker signal indicates the start of a new display frame. LFLM becomes
active after the last line pulse of the frame and remains active until the next line pulse, at which point
it deasserts and remains inactive until the next frame. The LFLM can be programmed to be an active
high or active low signal in software. See Section 8.3.10, “LCD Polarity Configuration Register,”
for more information.
• LLP—The LCD Line Pulse signal is used to latch a line of shifted data onto an LCD panel. The LLP
can be programmed to be an active high or active low signal in software. See Section 8.3.10, “LCD
Polarity Configuration Register,” for more information.
• LCLK—The LCD Shift Clock signal is the clock output to which the output data to the LCD panel
is synchronized. The LCLK can be programmed to be an active high or active low signal in
software. See Section 8.3.10, “LCD Polarity Configuration Register,” for more information.
• LACD—The LCD Alternate Crystal Direction output signal is toggled to alternate the crystal
polarization on the panel. This signal can be programmed to toggle for a period of 1 to 16 frames.
The LACD signal will toggle after a preprogrammed number of FLM or LP pulses. It can be
programmed so that the LACD will toggle once every 1 to N frames or LLP pulse. The targeted
number N is equal to the alternation code’s 7-bit value plus one. The default value for LACDRC is
0, which enables the LACD signal to toggle on every frame. See Section 8.3.11, “LACD Rate
Control Register,” for more information.
8.2.1.1 Panel Interface Timing
The LCD controller continuously passes the pixel data into the LCD panel via the LCD data bus. The bus
is timed by the LCLK, LLP, and LFLM signals. The LCLK signal clocks the pixel data into the display
drivers’ internal shift register. The LLP signal latches the shifted pixel data into a wide latch at the end of a
line, while the LFLM signal marks the first line of the displayed page.
The LCD controller is designed to support most monochrome LCD panels. Figure 8-2 on page 8-4
illustrates the LCD interface timing for 1-, 2-, and 4-bit LCD data bus operation. The LLP signal signifies
the end of the current line of serial data. The LLP signal enclosed by the LFLM signal marks the end of the
first line of the current frame.
Some LCD panels can use an active low LFLM, LLP, or LCLK signal and reversed pixel data. To change
the polarity of these signals, set the FLMPOL, LPPOL, LCKPOL, and PIXPOL bits in the LCD polarity
configuration (LPOLCF) register to 1. In addition to the interface timing pins, the LACD pin will toggle
after a preprogrammed number of LFLM pulses. The purpose of this pin is to prevent the crystal in the
LCD panel from degrading.