Motorola MC68VZ328 - Manual (Page 228)

12-4 MC68VZ328 User’s Manual
GP Timer Overview
12.1.5 Cascaded Timers
Both timers can be cascaded together to create a 32-bit counter. The cascade configuration is controlled by
the T[1:0] field of the PCR. See Section 5.2.2, “Peripheral Control Register,” on page 5-4 for more details.
Table 12-1 shows the two possible configurations of cascaded timers. When T[1:0] = 0x10, Timer 1 and
Timer 2 are cascaded together. Timer 1 becomes the MSW, and Timer 2 is the LSW. If the direction of the
pin is in (DIR6 = 0), the TIN signal is applied to Timer 2. If the direction is out (DIR6 = 1), the TOUT is
connected to Timer 1.
When T[1:0] = 0x11, Timer 2 becomes the MSW and Timer 1 is the LSW. If the direction of the pin is in
(DIR6 = 0), the TIN signal is applied to Timer 1. If the direction is out (DIR6 = 1), the TOUT is connected
to Timer 2.
12.1.5.1 Compare and Capture Using Cascaded Timers
When the timers are cascaded, the associated compare and capture registers are not. The flow diagram in
Figure 12-2 on page 12-5 suggests one method for 32-bit compares using a cascaded timer. Captures can
also be accomplished using the CAPT status bit instead of the COMP status bit.
After the compare to Timers 1 and 2 is written, the COMP or CAPT status bit of the MSW is checked.
When the MSW status bit sets, check the status bit of the LSW. If it is not set, loop until it does set.
Table 12-1. Cascade Timer Settings
T[1:0] PCR MSW LSW TIN To TOUT From
10 Timer 1 Timer 2 Timer 2 Timer 1
11 Timer 2 Timer 1 Timer 1 Timer 2