4 address bus signals, 5 data bus signals, Address bus signals -5 – Motorola MC68VZ328 User Manual
Page 47: Data bus signals -5
Data Bus Signals
Signal Descriptions
2-5
1.2 s before its voltage is higher than 1.2 V to ensure that the crystal oscillator starts and stabilizes.
See Section 4.3.1, “CLK32 Clock Signal,” on page 4-4 for details about selecting circuit values.
This signal is inactive while the CPU is executing the RESET instruction.
NOTE:
When an R/C circuit is being used to generate the RESET signal to the
MC68VZ328, the R/C circuit must be placed as close to the chip as
possible.
2.4
Address Bus Signals
The address bus pins A[23:0] are the address lines driven by the CPU or LCD controller for panel refresh
DMA. In sleep mode, all address signals are in an active state of the last bus cycle. Refer to
Section 4.5.1.4, “Sleep Mode,” on page 4-12 for more detailed information.
•
A0/PG1—Address 0 or Port G bit 1. After system reset, this signal defaults to A0.
•
MA[15:0]/A[16:1]—Multiplexed DRAM bits 15–0 or Address bits 16–1. These address output
lines are multiplexed with the DRAM row and column address signals. The MA signal is selected
on DRAM access cycles.
•
A[19:17]—Address lines 19–17.
•
A[23:20]/PF[6:3]—Address bits 23–20 or Port F bits 6–3. These address lines are multiplexed with
Port F. These signals default to address functions after reset.
2.5
Data Bus Signals
The flexible data bus interface design of the MC68VZ328 microprocessor allows programming of the
lower byte of the data bus (in an 8-bit-only system) to operate as general-purpose I/O signals. In sleep
mode, all of the data bus pins (D15–D0) are individually pulled up with 1-megaohm resistors. Refer to
Section 4.5.1.4, “Sleep Mode,” on page 4-12 for more detailed information.
•
D[15:8]—Data bits 15–8. The upper byte of the data bus is not multiplexed with any other signal.
In pure 8-bit systems, this is the data bus. In mixed 8- and 16-bit systems, 8-bit memory blocks or
peripherals should be connected to this bus.
•
D[7:0]/PA[7:0]—Data bits 7–0 or Port A bits 7–0. This bus is the lower data byte or general-purpose
I/O. In pure 8-bit systems, this bus can serve as a general-purpose I/O. The WDTH8 bit in the SCR
register (0xFFF000) should be set to 1 by software before the port can be used. See Section 5.2.1,
“System Control Register,” on page 5-2 for details on setting this bit. In 16-bit or mixed 8- and
16-bit systems, these pins must function as the lower data byte.