Motorola MC68VZ328 - Manual (Page 114)

7-4 MC68VZ328 User’s Manual
DRAM Controller Operation
Table 7-1. DRAM Address Multiplexing Options
A1/MD0 A2/MD1 A3/MD2 A4/MD3 A5/MD4 A6/MD5 A7/MD6 A8/MD7
Row
Address
Options
PA23
PA22
PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18
Column
Address
Options
PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8
Column
Address
Options
for
SDRAM
PA1 1
PA0
1.Pin A1/MD0 has column address options of PA0 and PA1 for SDRAM. The SCOL bit (bit 6) of the SDRAM control
register (0xFFFFFC04) determines the selection. When SCOL = 0, PA1 is selected. When SCOL = 1, PA0 is se-
lected.
PA2 PA3 PA4 PA5 PA6 PA7 PA8
MD
Address
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
A9/MD8 A10/MD9 A11/MD10 A12/MD11 A13/MD12 A14/MD13 A15/MD14 A16/MD15
Row
Address
Options
PA10
PA20 PA9
PA19
PA19
PA21 PA20
PA22 PA10
PA21
PA23 PA22 PA23 PA24
Column
Address
Options
PA0
(PA1)
PA9
PA0
PA10
PA0
PA11
PA12 PA13 PA22 PA23 PA24
Column
Address
Options
for
SDRAM
PA1 2
PA9
2.Pin A9/MD8 has column address options of PA1 and PA9 for SDRAM. The COL8 bit (bit 5) of the DRAM memory
configuration register (0xFFFFFC00) determines the selection. When COL8 = 0, PA9 is selected. When COL8 = 1,
PA1 is selected.
PA1 0 PA20 3
PA22
3.Pin A12/MD11 has column address options of PA20 and PA22 for SDRAM. The ROW11 bit (bit 11) of the DRAM
memory configuration register (0xFFFFFC00) determines the selection. When ROW11 = 0, PA20 is selected.
When ROW11 = 1, PA22 is selected.
PA10 4
PA21
PA23
4.Pin A13/MD12 has column address options of PA10, PA21, and PA23 for SDRAM. The ROW12 field (bits 15–14)
of the DRAM memory configuration register (0xFFFFFC00) determines the selection. When ROW12 = 00, PA10 is
selected. When ROW12 = 01, PA21 is selected. When ROW12 = 10, PA23 is selected.
PA22 PA23 PA24
MD
Address
MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15