Motorola MC68VZ328 - Manual (Page 362)

Index-iv MC68VZ328 User’s Manual
CTSD bit
USTCNT1 register, 14-11
USTCNT2 register, 14-21
CTSx pin, programming to post interrupt, 14-3
CUPS2 bit, 6-18
Cursor control 1 and 0 field, see CCx field
Cursor height 4–0 field, see CHx field
Cursor vertical Y pixel 8–0 field, see CYPx field
Cursor width 4–0 field, see CWx field
Cursor X position 9–0 field, see CXPx field
CWSO bit, 6-17
CWx field, 8-14
CXPx field, 8-13
CYPx field, 8-13
D
D[15:8] pins, 2-5
D[7:0]/PA[7:0] pins, 2-5
Data and address mode types, see CPU
Data b-record format, see bootstrap mode
Data bus
mixing 16- and 8-bit address devices, 6-3
programming bus width, 6-3
selecting initial width, 6-3
signals
data bits 15–8, see D[15:8] pins
data bits 7–0, see D[7:0]/PA[7:0] pins
introduction, 2-5
Port A bits 7–0, see D[7:0]/PA[7:0] pins
Data bus width bit, see BSW bit
Data bus width, boot device operation, 9-5
DATA field
SPIDATA2 register, 13-14
SPIRXD register, 13-4
SPITXD register, 13-5
Data field, see Dx field
DATA RATE field
SPICONT1, 13-6
SPICONT2 register, 13-15
Data ready (FIFO status) bit, see DATA READY bit
DATA READY bit
URX1 register, 14-13
URX2 register, 14-23
DATA_READY control field, see DRCTL field
DATA_READY signal, 13-3
DC characteristics, see electrical characteristics
Definitions, general, xxx
DGBA field, 6-7
Direction field, see DIRx field
DIRx field
PADIR register, 10-7
PBDIR register, 10-9
PCDIR register, 10-12
PDDIR register, 10-16
PEDIR register, 10-21
PFDIR register, 10-24
PGDIR register, 10-28
PJDIR register, 10-31
PKDIR register, 10-34
PMDIR register, 10-37
Disable PLL bit, see DISPLL bit
DISPLL bit, 4-9
DIVIDE field
UBAUD1 register, 14-12
UBAUD2 register, 14-22
DMA burst length field, see DMABL[3:0] field
DMA control register, see DMACR register
DMA trigger mark field, see DMATM[2:0] field
DMABL[3:0] field, 8-22
DMACR register, 8-22
DMATM[2:0] field, 8-22
Doze mode
operation, 4-11
recommended power settings, 4-11
DRAM bit, 6-14
DRAM control register, see DRAMC register
DRAM controller
block diagram, 7-2
collisions, 7-8
data retention during reset, 7-10
data retention sequence, 7-11
DTACK (description), 7-8
features, 7-1
operation
8-bit mode, 7-9
address multiplexing, 7-3
low-power standby mode, 7-9
PAGE_ACCESS signal from LCD controller, 7-8
refresh
control, 7-7
example values, 7-7
timing diagrams, 19-8 to 19-31
DRAM memory configuration register, see DRAMMC
register
DRAM selection bit, see DRAM bit
DRAM write-enable, see DWE/UCLK/PE3 pin
DRAMMC register, 7-12
DRCTL field, 13-6
DS toggle enable bit, see DST bit
DSIZ3 bit, 6-17
DST bit, 6-20
DTACK generation, 7-7
DUPS2 bit, 6-17
DWE/UCLK/PE3 pin, 2-6
DWSO bit, 6-17
Dx field
PADATA register, 10-7
PBDATA register, 10-9