Motorola MC68VZ328 - Manual (Page 242)

13-6 MC68VZ328 User’s Manual
SPI 1 Programming Model
13.3.3 SPI 1 Control/Status Register
This register controls the configuration and operation of the SPI 1 module. The bit position assignments for
this register are shown in the following register display. The settings for this register are described in
Table 13-3.
SPICONT1 SPI 1 Control/Status Register 0x(FF)FFF704
BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
DATA RATE DRCTL MODE SPIEN XCH
SS
POL
SS
CTL
PHA POL BIT COUNT
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 13-3. SPI 1 Control/Status Register Description
Name Description Setting
DATA RATE
Bits 15–13 Data Rate—This field selects the bit rate of the
SCLK based on the division of the system
clock. The master clock for SPI 1 in master
mode is SYSCLK. 000 = Divide SYSCLK by 4
001 = Divide SYSCLK by 8
010 = Divide SYSCLK by 16
011 = Divide SYSCLK by 32
100 = Divide SYSCLK by 64
101 = Divide SYSCLK by 128
110 = Divide SYSCLK by 256
111 = Divide SYSCLK by 512
DRCTL
Bits 12–11 DATA_READY Control—In master mode,
these 2 bits select the waveform of the
DATA_READY input signal. In slave mode,
they have no effect. 00 = Don’t care DATA_READY
01 = Falling edge trigger input
10 = Active low level trigger input
11 = RSV
MODE
Bit 10 SPI 1 Mode Select—This bit selects the mode
of SPI 1. 0 = SPI 1 is slave mode
1 = SPI 1 is master mode
SPIEN
Bit 9 SPI 1 Enable—This bit enables SPI 1. This bit
must be asserted before initiating an
exchange. Writing a 0 to this bit flushes the Rx
and Tx FIFOs. 0 = Serial peripheral interface is disabled
1 = Serial peripheral interface is enabled
XCH
Bit 8 Exchange—In master mode, writing a 1 to this
bit triggers a data exchange. This bit remains
set while either the exchange is in progress or
SPI 1 is waiting for active DATA_READY input
while DATA_READY is enabled. This bit is
cleared automatically when all data in the
TxFIFO and shift registers are shifted out. In
slave mode, this bit must be clear. 1 = Initiates exchange (write) or busy (read)
0 = Idle
SSPOL
Bit 7 SS Polarity Select—In both master and slave
modes, this bit selects the polarity of SS signal. 0 = Active low
1 = Active high