4 cgm programming model, 1 pll control register, Cgm programming model -8 – Motorola MC68VZ328 User Manual
Page 76: Pll control register -8, Table 4-2, Pll control register description -8
4-8
MC68VZ328 User’s Manual
CGM Programming Model
4.4
CGM Programming Model
This section describes the two registers that enable and control the frequency of the CGM clocks.
4.4.1
PLL Control Register
The PLL control register (PLLCR) controls the frequency selection of the LCDCLK, SYSCLK, and
DMACLK. It also enables the output of the PLL and clock out/Port F pin 2 (CLKO/PF2). The settings for
each bit and field in the register are described in Table 4-2.
PLLCR
PLL Control Register
0xFFFFF200
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
LCDCLK SEL
SYSCLK SEL
PRESC1
PRESC2
CLKEN
DISPLL
WKSEL
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0x24B3
Table 4-2. PLL Control Register Description
Name Description
Setting
Reserved
Bits 15–14
Reserved
These bits are reserved and should be set to
0.
LCDCLK SEL
Bits 13–11
LCD Clock Select—This field controls the
divide ratio used by the LCD clock divider to
convert DMACLK to LCDCLK. This field can
be changed at any time.
000 = DMACLK ÷ 2.
001 = DMACLK ÷ 4.
010 = DMACLK ÷ 8.
011 = DMACLK ÷ 16.
1xx = DMACLK ÷ 1 (%100 after reset).
SYSCLK SEL
Bits 10–8
System Clock Select—This field controls the
divide ratio used by the SYSCLK divider to
convert DMACLK to SYSCLK. This field can
be changed at any time.
000 = DMACLK ÷ 2.
001 = DMACLK ÷ 4.
010 = DMACLK ÷ 8.
011 = DMACLK ÷ 16.
1xx = DMACLK ÷ 1 (%100 after reset).
PRESC1
Bit 7
Prescaler 1 Select—This bit selects the divide
ratio of the prescaler 1.
0 = PLLCLK ÷ 1.
1 = PLLCLK ÷ 2 (default).
Reserved
Bit 6
Reserved
This bit is reserved and should be set to 0.
PRESC2
Bit 5
Prescaler 2 Select—This bit selects the divide
ratio used by the prescaler 2 to divide the out-
put of prescaler 1, producing DMACLK. This
field can be changed at any time.
0 = PR1CLK ÷ 1.
1 = PR1CLK ÷ 2 (default).
CLKEN
Bit 4
Clock Enable—This bit enables the buffered
output of the SYSCLK at the CLKO/PF2 pin
when bit 2 of the PFSEL register is also
cleared.
0 = CLKO enabled.
1 = CLKO disabled (default).