3 modules of the mc68vz328, 1 memory controller, 2 clock generation module and power control module – Motorola MC68VZ328 User Manual

Page 38: Modules of the mc68vz328 -8, Memory controller -8

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1-8

MC68VZ328 User’s Manual

Modules of the MC68VZ328

1.3

Modules of the MC68VZ328

In addition to the powerful 68000 processor, the DragonBall VZ contains a wide variety of peripheral
interface and control modules. The following subsections provide brief descriptions of these modules and
how they operate.

1.3.1

Memory Controller

The memory controller provides a glueless interface to most memory chips on the market. It supports flash,
ROM, SRAM, different DRAM types (EDO RAM and Fast Page Mode), and synchronous DRAM. Either
one or two banks of DRAM may be used, and each bank can be a maximum of 32 Mbyte. For a more
complete explanation of how memory is configured and controlled, see Chapter 3, “Memory Map.”

1.3.2

Clock Generation Module and Power Control Module

The module containing the clock synthesizer operates with either an external crystal or an external
oscillator to provide a stable clock source for the internal clock generation module (CGM). The output
frequency can be adjusted by writing to the CGM frequency select register. The CGM can be disabled to
shut down the system clock divider chain for maximum power saving, while the real-time clock (RTC) and
DRAM controller remain active. The power control module can be configured to control the CPU cycles to
optimize power consumption. The power control module offers three power-saving modes: normal, doze,

EORI

Exclusive OR immediate

STOP

Stop

EORI to CCR

Exclusive OR immediate to condition codes

SUB

Subtract

EORI to SR

Exclusive OR immediate to status register

SUBA

Subtract address

EXG

Exchange registers

SUBI

Subtract immediate

EXT

Sign extend

SUBQ

Subtract quick

JMP

Jump

SUBX

Subtract with extend

JSR

Jump to subroutine

SWAP

Swap data register halves

LEA

Load effective address

TAS

Test and set operand

LINK

Link stack

TRAP

Trap

LSL

Logical shift left

TRAPV

Trap on overflow

LSR

Logical shift right

TST

Test

MOVE

Move

UNLK

Unlink

MOVEA

Move address

Table 1-2. Instruction Set (Continued)

Mnemonic

Description

Mnemonic

Description

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