Motorola MC68VZ328 - Manual (Page 360)

Index-ii MC68VZ328 User’s Manual
reset timing diagram, 17-2
setting up RS-232 terminal, 17-3
Break (character status) bit, see BREAK bit
BREAK bit
URX1 register, 14-14
URX2 register, 14-24
Break characters, generating, 14-5
BSW bit
CSA register, 6-8
CSB register, 6-10
CSC register, 6-12
CSD register, 6-15
BUPS2 bit, 6-18
Burst mode
during wake-up event, 4-13
operation, 4-12
operational example, 4-13
setting the PEN bit, effects of, 4-11
Bus control signals
bus width, see BUSW/DTACK/PG0 pin
data strobe signals, see UDS/PK3, LDS/PK2 pin
data transfer acknowledge, see
BUSW/DTACK/PG0 pin
DRAM write-enable, see DWE/UCLK/PE3 pin
introduction, 2-6
lower byte write-enable, see LWE/LB pin
output enable, see OE pin
Port E bit 3, see DWE/UCLK/PE3 pin
Port G bit 0, see BUSW/DTACK/PG0 pin
read/write signal, see RW/PK1 pin
UART clock, see DWE/UCLK/PE3 pin
upper byte write-enable, see UWE/UB pin
BUSW/DTACK/PG0 pin, 2-6
Busy (Tx status) bit, see BUSY bit
BUSY bit
UTX1 register, 14-15
UTX2 register, 14-25
BWSO bit, 6-17
C
CAP field
TCTL1 register, 12-7
TCTL2 register, 12-7
CAPT bit
TSTAT1 register, 12-12
TSTAT2 register, 12-12
Capture edge field, see CAP field
Capture event bit, see CAPT bit
Capture events, 12-2
CAPTURE field
TCR1 register, 12-10
TCR2 register, 12-10
Capture value field, see CAPTURE field
CAS0/CAS1 signal, 6-1
Cascaded timers
available configurations, 12-4
description of, 12-4
methods to compare and capture, 12-4
CCPEN bit, 8-21
CCx field, 8-12
CGBA field, 6-7
CGM, see clock generation module
Chip ID and version, determining, 18-1
Chip-select
and EDO RAM interface signals, 2-10
logic
address select signal, see AS signal
configuring memory, 6-2
data bus size programming, 6-3
during reset, 9-4
group base address registers A–D,
overview, 6-1
memory devices supported, 6-1
memory protection, 6-2
memory size ranges, 6-2
memory size selection, 6-2
overlapping registers, hazards of, 6-4
overview, 6-1 to 6-2
unprotected memory size calculation, 6-18
registers
control register 1, see CSCTRL1 register
control register 2, see CSCTRL2 register
control register 3, see CSCTRL3 register
group A base address register, see CSGBA
register
group B base address register, see CSGBB
register
group C base address register, see CSGBC
register
group D base address register, see CSGBD
register
register A, see CSA register
register B, see CSB register
register C, see CSC register
register D, see CSD register
upper group base address register, see
CSUGBA register
timing
flash write cycle timing, 19-6
read cycle timing, 19-3
timing parameters referenced to CLKO
reference, 19-3
timing trim, 19-8
write cycle timing, 19-5
Chip-select enable bit, see EN bit
Chip-select size field, see SIZ field
CHx field, 8-14
CLK bit, 7-14