Motorola MC68VZ328 - Manual (Page 195)

Programming Model
I/O Ports 10-25
10.4.7.2 Port F Data Register
The settings for the bit positions of the PFDATA register are shown in Table 10-32.
PFDATA Port F Data Register 0x(FF)FFF429
Port F is multiplexed with address lines A[23:20] and several dedicated functions. These pins can be
programmed as GPIO when the address bus and the dedicated I/O signals are not in use.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
BIT 7 6 5 4 3 2 1 BIT 0
D7 D6 D5 D4 D3 D2 D1 D0
TYPE rw rw rw rw rw rw rw rw
RESET
1 1 1 1 1 1 1 1
0xFF*
*Actual bit value depends on external circuits connected to pin.
Table 10-32. Port F Data Register Description
Name Description Setting
Dx
Bits 7–0 Data—These bits reflect the
status of the I/O signal in an
8-bit system. 0 = Drives the output signal low when DIRx is set to 1 or the external
signal is low when DIRx is set to 0
1 = Drives the output signal high when DIRx is set to 1 or the external
signal is high when DIRx is set to 0