Motorola MC68VZ328 - Manual (Page 273)

Programming Model
Universal Asynchronous Receiver/Transmitter 1 and 2 14-21
ODEN
Bit 7 Old Data Enable—This bit enables an interrupt when the OLD
DATA bit in the URX register is set. 0 = OLD DATA interrupt is disabled
1 = OLD DATA interrupt is enabled
CTSD
Bit 6 CTS2 Delta Enable—When this bit is high, it enables an inter-
rupt when the CTS2 pin changes state. When it is low, this
interrupt is disabled. The current status of the CTS2 pin is read
in the UTX register. 0 = CTS2 interrupt is disabled
1 = CTS2 interrupt is enabled
RXFE
Bit 5 Receiver Full Enable—When this bit is high, it enables an
interrupt when the receiver FIFO is full. This bit resets to 0. 0 = RX FULL interrupt is disabled
1 = RX FULL interrupt is enabled
RXHE
Bit 4 Receiver Half Enable—When this bit is high, it enables an
interrupt when the receiver FIFO is more than half full. This bit
resets to 0. 0 = RX HALF interrupt is disabled
1 = RX HALF interrupt is enabled
RXRE
Bit 3 Receiver Ready Enable—When this bit is high, it enables an
interrupt when the receiver has at least 1 data byte in the FIFO.
When it is low, this interrupt is disabled. 0 = RX interrupt is disabled
1 = RX interrupt is enabled
TXEE
Bit 2 Transmitter Empty Enable—When this bit is high, it enables
an interrupt when the transmitter FIFO is empty and needs
data. When it is low, this interrupt is disabled. 0 = TX EMPTY interrupt is disabled
1 = TX EMPTY interrupt is enabled
TXHE
Bit 1 Transmitter Half Empty Enable—When this bit is high, it
enables an interrupt when the transmit FIFO is less than half
full. When it is low, the TX HALF interrupt is disabled. This bit
resets to 0. 0 = TX HALF interrupt is disabled
1 = TX HALF interrupt is enabled
TXAE
Bit 0 Transmitter Available for New Data—When this bit is high, it
enables an interrupt if the transmitter has a slot available in the
FIFO. When it is low, this interrupt is disabled. This bit resets to
0. 0 = TX AVAIL interrupt is disabled
1 = TX AVAIL interrupt is enabled
Table 14-10. UART 2 Status/Control Register Description (Continued)
Name Description Setting