Motorola MC68VZ328 - Manual (Page 137)

LCD Controller Operation
LCD Controller 8-9
During the same period, the line buffer must be filled. The following T
DMA
duration is how long the DMA
cycle will hold up the bus:
Thus, the percentage of host bus time taken up by the LCD controller’s DMA is P
DMA
:
8.2.5 Self-Refresh Mode
The LCD driver from Epson was used as a reference for the design of the refresh mode. In self-refresh
mode, the LCD module will update the screen periodically from internal RAM using the LP and FRM
pulse.
8.2.5.1 Entering Self-Refresh Mode
Setting the self-refresh register bit 7 to 1 means that the LSCLK and LD will remain 0 when the end of the
frame is reached. The LP and FRM pulse continue as in normal mode, but there are no pulses on either the
LSCLK or LD.
8.2.5.2 Canceling Self-Refresh Mode
Setting the self-refresh register bit 7 to 0 means that the normal mode is entered when the end of the frame
is reached. On entering normal mode, data is sent out from the beginning of the page.
T
l
1
60 Hz
---------------
1
240 lines
----------------------
×
=
69.4
µ
s =
T
DMA
320 pixels 2 bits per pixel
×
2 clocks
×
16.67 MHz 16-bit bus
×
----------------------------------------------------------------------------------------------------- =
4.8
µ
s =
P
DMA
4.8‘
µ
s
69.4‘
µ
s
--------------------- =
6.92‘% =