Motorola MC68VZ328 - Manual (Page 81)

Introduction to the Power Control Module
Clock Generation Module and Power Control Module 4-13
Figure 4-4. Power Control Module Block Diagram
If a wake-up event occurs while CPUCLK is disabled, the PCM is disabled and CPUCLK is immediately
restored, allowing the CPU to process the event. The DMA controller always has priority, so if a DMA
access is in progress, the CPU will wait until the DMA controller has completed its access before servicing
the wake-up routine. Note that the LCD DMA controller has access to the bus at all times and the SYSCLK
(master clock to all peripherals) is continuously active.
Figure 4-5 illustrates how the PCM operates. As described previously, a width setting of %11111
represents 31 periods of CLK32, or approximately 1 ms. In this example, the width setting in the PCTLR is
00011. The clock bursts are applied at a burst width of three thirty-firsts, or approximately at 10 percent on
time, making the CPU active about 10 percent of the time. The remainder of the time, the CPU is in doze
mode. When a wake-up event occurs, CPUCLK immediately returns to 100 percent so the CPU can service
the wake-up event interrupt.
Figure 4-5. Power Control Operation in Burst Mode
Burst-Width
Control
CLK32
SYSCLK
Clock
Control
CPUCLK
CPU Interface
CPU Bus
Request CPU Bus
CPU Bus
Grant
DMA Bus
Grant
DMA Bus
Request
Wake-up
PCTLR
Width
SYSCLK
CPUCLK
PCEN
CPU Active CPU Inactive CPU Active Wake-up Event CPU Inactive
Enabled Disabled
CPU Active
CLK32
31 cycles
1 ms
Clock Burst Width = %00011