Motorola MC68VZ328 - Manual (Page 252)

13-16 MC68VZ328 User’s Manual
SPI 2 Programming Model
IRQEN
Bit 6 Interrupt Request Enable—This bit enables
an interrupt to be generated when an SPI 2
module exchange is finished. This bit does not
affect the operation of the IRQ bit; it only
affects the interrupt signal to the interrupt con-
troller. 0 = Disable interrupt generation.
1 = Allow interrupt generation.
PHA
Bit 5 Phase—This bit controls the clock and data
phase relationship. 0 = Phase 0 operation.
1 = Phase 1 operation.
POL
Bit 4 Polarity—This bit controls the polarity of the
SCLK signal. 0 = Active high polarity (0 = idle).
1 = Active low polarity (1 = idle).
BIT COUNT
Bits 3–0 Bit Count—This field selects the length of the
transfer. A maximum of 16 bits can be trans-
ferred.
In master mode, a 16-bit data word is loaded
from the TxFIFO to the shift register, and only
the least significant n bits (n = BIT COUNT)
are shifted out. The next 16-bit word is then
loaded to the shift register.
In slave mode (when the SSCTL bit is 0), this
field controls the number of bits received as a
data word loaded to the RxFIFO. When the
SSCTL bit is 1, this field is ignored.
0000 = 1-bit transfer.
0001 = 2-bit transfer.
.
.
.
1110 = 15-bit transfer.
1111 = 16-bit transfer.
Table 13-8. SPI 2 Control/Status Register Description (Continued)
Name Description Setting