Motorola MC68VZ328 - Manual (Page 370)

Index-xii MC68VZ328 User’s Manual
bit 4, see RXD1/PE4 pin
bit 5, see TXD1/PE5 pin
bit 6, see RTS1/PE6 pin
dedicated I/O functions, 10-22
registers
data register, see PEDATA register
direction register, see PEDIR register
pull-up enable register, see PEPUEN register
register summary, 10-21
select register, see PESEL register
Port F
bit 0, see LCONTRAST/PF0 pin
bit 2, see CLKO/PF2 pin
dedicated I/O functions, 10-25
registers
data register, see PFDATA register
direction register, see PFDIR register
pull-up enable register, see PFPUEN register
register summary, 10-24
select register, see PFSEL register
Port G
bit 1, see A0/PG1 pin
dedicated I/O functions, 10-29
operational considerations, 10-30
registers
data register, see PGDATA register
direction register, see PGDIR register
pull-up enable register, see PGPUEN register
register summary, 10-28
select register, see PGSEL register
Port J
bit 0, see MOSI/PJ0 pin
bit 1, see MISO/PJ1 pin
bit 2, see SPICLK1/PJ2 pin
bit 3, see SS/PJ3 pin
bit 4, see RXD2/PJ4 pin
bit 5, see TXD2/PJ5 pin
bit 7, see RTS2/PJ6 pin
dedicated I/O functions, 10-32
registers
data register, see PJDATA register
direction register, see PJDIR register
pull-up enable register, see PJPUEN register
register summary, 10-31
select register, see PJSEL register
Port K
bit 0, see PWMO2/DATA_READY/PK0 pin
bits 7–4, see LD[3:0]/PC[3:0], LD[7:4]/PK[7:4]
pins
dedicated I/O functions, 10-35
registers
data register, see PKDATA register
direction register, see PKDIR register
pull-up/pull-down enable register, see
PKPUEN register
register summary, 10-34
select register, see PKSEL register
Port M
dedicated I/O functions, 10-39
registers
data register, see PMDATA register
direction register, see PMDIR register
pull-up/pull-down enable register, see
PMPUEN register
register summary, 10-37
select register, see PMSEL register
POSx field, 8-19
Power control enable bit, see PCEN bit
Power control module (PCM)
introduction, 4-10
modes of operation
burst, 4-11
normal, 4-11
sleep, 4-12
waking up, 9-20
Power control register , see PCTLR register
PRESC1 bit, 4-8
PRESC2 bit, 4-8
Prescaler 1 select bit, see PRESC1 bit
Prescaler 2 select bit, see PRESC2 bit
PRESCALER bit, 15-4
PRESCALER field
UBAUD1 register, 14-12
UBAUD2 register, 14-22
Prescaler selection bit, see PRESEL bit
PRESEL bit
NIPR1 register, 14-18
NIPR2 register, 14-28
Programmer’s memory map
diagram, 3-1
introduction, 3-1
sorted by address, 3-2 to 3-7
sorted by register name, 3-8 to 3-13
Programming examples
bootstrap system initialization, 17-4
chip-select initialization, 6-21
configuring PLLCLK frequency, 4-7
LCD controller, 8-22
power control shutdown, 4-12
Programming model
CGM, 4-8 to 4-10
chip-select, 6-4 to 6-21
CPU, 1-5 to 1-8
DRAM controller, 7-12 to 7-18
GP timers, 12-6 to 12-12
I/O ports, 10-6 to 10-40
ICE module, 16-4 to 16-14