Motorola MC68VZ328 - Manual (Page 161)

Programming Model
Interrupt Controller 9-11
MIRQ2
Bit 17 Mask IRQ2 Interrupt—When set, this bit indicates that IRQ2
is masked. It is set to 1 after reset. 0 = Enable IRQ2 interrupt.
1 = Mask IRQ2 interrupt.
MIRQ1
Bit 16 Mask IRQ1 Interrupt—When set, this bit indicates that IRQ1
is masked. It is set to 1 after reset. 0 = Enable IRQ1 interrupt.
1 = Mask IRQ1 interrupt.
Reserved
Bits 15–14 Reserved These bits are reserved and should
be set to 0.
MPWM2
Bit 13 Mask PWM 2 Interrupt—When set, this bit indicates that
PWM 2 is masked. It is set to 1 after reset. 0 = Enable pulse-width modulator 2
interrupt.
1 = Mask pulse-width modulator 2
interrupt.
MUART2
Bit 12 Mask UART 2 Interrupt—When set, this bit indicates that
UART 2 is masked. It is set to 1 after reset. 0 = Enable UART 2 interrupt.
1 = Mask UART 2 interrupt.
MINT3
Bit 11 Mask External INT3 Interrupt—Setting this bit masks the
INT3 interrupt. It is set to 1 after reset. 0 = Enable INT3 interrupt.
1 = Mask INT3 interrupt.
MINT2
Bit 10 Mask External INT2 Interrupt—Setting this bit masks the
INT2 interrupt. It is set to 1 after reset. 0 = Enable INT2 interrupt.
1 = Mask INT2 interrupt.
MINT1
Bit 9 Mask External INT1 Interrupt—Setting this bit masks the
INT1 interrupt. It is set to 1 after reset. 0 = Enable INT1 interrupt.
1 = Mask INT1 interrupt.
MINT0
Bit 8 Mask External INT0 Interrupt—Setting this bit masks the
INT0 interrupt. It is set to 1 after reset. 0 = Enable INT0 interrupt.
1 = Mask INT0 interrupt.
MPWM1
Bit 7 Mask PWM 1 Interrupt—Setting this bit masks the PWM 1
interrupt. It is set to 1 after reset. 0 = Enable pulse-width modulator 1
interrupt.
1 = Mask pulse-width modulator 1
interrupt.
MKB
Bit 6 Mask Keyboard Interrupt—Setting this bit masks the key-
board interrupt. It is set to 1 after reset. 0 = Enable keyboard interrupt.
1 = Mask keyboard interrupt.
MTMR2
Bit 5 Mask Timer 2 Interrupt—Setting this bit masks the timer
interrupt. It is set to 1 after reset. 0 = Enable timer 2 interrupt.
1 = Mask timer 2 interrupt.
MRTC
Bit 4 Mask RTC Interrupt—Setting this bit masks the real-time
clock (time of day) interrupt. It is set to 1 after reset. 0 = Enable real-time clock interrupt.
1 = Mask real-time clock interrupt.
MWDT
Bit 3 Mask Watchdog Timer Interrupt—Setting this bit masks the
watchdog timer interrupt. It is set to 1 after reset. 0 = Enable watchdog timer
interrupt.
1 = Mask watchdog timer interrupt.
MUART1
Bit 2 Mask UART 1 Interrupt—When set, this bit indicates that
UART 1 is masked. It is set to 1 after reset. 0 = Enable UART 1 interrupt.
1 = Mask UART 1 interrupt.
MTMR1
Bit 1 Mask Timer 1 Interrupt—Setting this bit masks the timer
interrupt. It is set to 1 after reset. 0 = Enable timer 1 interrupt.
1 = Mask timer 1 interrupt.
MSPI2
Bit 0 Mask SPI 2 Interrupt—When set, this bit indicates that the
SPI 2 interrupt is masked. It is set to 1 after reset. 0 = Enable SPI 2 interrupt.
1 = Mask SPI 2 interrupt.
Table 9-5. Interrupt Mask Register Description (Continued)
Name Description Settings