Motorola MC68VZ328 - Manual (Page 256)

14-4 MC68VZ328 User’s Manual
UART Operation
• RXD1/RXD2—The Receive Data signal, which is multiplexed with PE4 (PJ4 in UART 2), is the
receiver serial input. As for the TXDx pin, while the UART is in NRZ mode, standard NRZ data is
expected. In IrDA mode, a pulse of at least 1.63
µ
s is expected for each zero bit received. The
required pulse polarity is controlled by the RXPOL bit of the corresponding UART miscellaneous
(UMISC) register. This pin interfaces to standard RS-232 and infrared transceiver modules.
• RTS1/RTS2—The Request to Send signal, which is multiplexed with PE6 (PJ6 in UART 2), serves
two purposes. Normally, this signal is used for flow control, in which the receiver indicates that it
is ready to receive data by asserting this pin (low). This pin is then connected to the far-end
transmitter’s CTS pin. When the receiver FIFO is nearly full (four slots are remaining), which
indicates a pending FIFO overrun, this pin is negated (high). When not being used for flow control,
this pin can be used as a general-purpose output controlled by the RTS1 bit (RTS2 bit in UART 2)
of the corresponding UMISC register.
• UCLK—The UART Clock input/output signal serves two purposes. It can serve as the source of the
clock to the baud rate generator, or it can output the bit clock at the selected baud rate for
synchronous operation. The external UCLK pin connects to the UCLK of both UART 1 and
UART 2. For UCLK output, only one UART at a time is selected to drive this signal. Please refer to
Section 5.2.2, “Peripheral Control Register,” on page 5-4 for more details.
14.3 UART Operation
Both UART modules consist of three sub-blocks:
• Transmitter
• Receiver
• Baud rate generator
Section 14.3.1, “Transmitter Operation,” through Section 14.3.3, “Baud Rate Generator Operation,”
discuss these sub-blocks in detail.
14.3.1 Transmitter Operation
The transmitter accepts a character (byte) from the CPU bus and transmits it serially. While the FIFO is
empty, the transmitter outputs a continuous idle (which is 1 bit in NRZ mode and selectable polarity in
IrDA mode). When a character is available for transmission, the start, stop, and parity (if enabled) bits are
added to the character, and it is serially shifted (LSB first) at the selected bit rate. The transmitter presents
a new bit on each falling edge of the bit clock.
14.3.1.1 TxFIFO Buffer Operation
The transmitter posts a maskable interrupt when it needs parallel data (TX AVAIL). There are three
maskable interrupts. To take maximum advantage of the 8-byte FIFO (64-byte FIFO in UART 2), the
FIFO EMPTY interrupt should be enabled. The interrupt service routine should load data until the
TX AVAIL bit in the UTX register is clear or until there is no more data to transmit. The transmitter does
not generate another interrupt until the FIFO has completely emptied.