1 cpu programming model, Cpu programming model -5, Figure 1-2 – Motorola MC68VZ328 User Manual
Page 35: User programming model -5, Figure 1-3, Supervisor programming model supplement -5
CPU
Introduction
1-5
1.2.1
CPU Programming Model
The CPU has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2. The first eight
registers (D7–D0) are data registers that are used for byte (8-bit), word (16-bit), and long-word (32-bit)
operations. When being used to manipulate data, the data registers affect the status register (SR). The next
seven registers (A6–A0) and the user stack pointer (USP) can function as software stack pointers and base
address registers. These registers can be used for word and long-word operations, but they do not affect the
status register. The D7–D0 and A6–A0 registers can be used as index registers.
Figure 1-2. User Programming Model
In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP) can also be
programmed, as shown in Figure 1-3.
Figure 1-3. Supervisor Programming Model Supplement
The status register contains the interrupt mask with seven available levels, as well as an extend (X),
negative (N), zero (Z), overflow (V), and carry (C) condition code. The T bit indicates when the processor
is in trace mode, and the S bit indicates when it is in supervisor or user mode.
Data Registers
Address Registers
31
16 15
8
7
0
User Stack Pointer
A7 (USP)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
0
15
16
31
31
16 15
0
31
0
0
PC
Program Counter
Status Register
SR
7
Supervisor Stack
A7 (SSP)
31
16 15
0
Pointer
15
0
7
8
SR
Status Register