3 chip-select write cycle timing, Chip-select write cycle timing -5, Figure 19-3 – Motorola MC68VZ328 User Manual
Page 321: Chip-select write cycle timing diagram -5
AC Electrical Characteristics
Electrical Characteristics
19-5
19.3.3
Chip-Select Write Cycle Timing
Figure 19-3 shows the write cycle timing used by chip-select. The signal values and units of measure for
this figure are found in Table 19-5 on page 19-6. For detailed information about the individual signals, see
Chapter 6, “Chip-Select Logic.”
Figure 19-3. Chip-Select Write Cycle Timing Diagram
11
CSx
negated to UB/LB negated (16-bit SRAM)
10
—
ns
Note:
n is the number of wait states in the current memory access cycle.
T is the system clock period.
The external DTACK input requirement is eliminated when CSx is programmed to use internal DTACK.
CSx stands for CSA0, CSA1, CSB0, CSB1, CSC0, CSC1, CSD0, or CSD1.
A value in parentheses is used when early cycle detection is turned on.
Table 19-4. Chip-Select Read Cycle Timing Parameters (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
A[31:0]
CSx
UWE/LWE
OE
D[15:0]
DTACK
UDS/LDS
UB/LB
WE
1
5
6
2
3
8
9
4
7
10
11