Motorola MC68VZ328 - Manual (Page 374)

Index-xvi MC68VZ328 User’s Manual
programming with ENABLE bit
disabling writes, 13-14
setting before changing other bits, 13-12
registers
control/status register, see SPICONT2 register
data register, see SPIDATA2 register
signals
clock pin, see SPICLK2 pin
introduction, 2-9
SPI master clock, see SPICLK2/PE2 pin
SPI master receive data, see SPIRXD/PE1 pin
SPI master transmit data, see SPITXD/PE0 pin
timing diagrams, generic, 13-12, 19-32
using GPIO as chip-select, 13-13
SPI unit 2 interrupt pending bit, see SPI2 bit
SPI unit 2 interrupt status bit, see SPI2 bit
SPI, introduction, 13-1
SPI1 bit
IPR register, 9-16
ISR register, 9-13
SPI2 bit
IPR reigster, 9-18
ISR register, 9-15
SPICLK1 signal, 13-3
SPICLK1/PJ2 pin, 2-9
SPICLK2 pin, 13-13
SPICLK2/PE2 pin, 2-9
SPICONT1 register, 13-6
SPICONT2 register, 13-15
SPIDATA2 register
description, 13-14
timing, 13-14
SPIEN bit, 13-6
SPIINTCS register, 13-8
SPIRXD register, 13-4
SPIRXD/PE1 pin, 2-9
SPISPC register, 13-11
SPITEST register, 13-10
SPITXD register, 13-5
SPITXD/PE0 pin, 2-9
SR16 bit, 6-17
SRC1–0 field, 8-20
SS polarity select bit, see SSPOL bit
SS signal, 13-3
SS waveform select bit, see SSCTL bit
SS/PJ3 pin, 2-9
SSAx field, 8-10
SSCTL bit, 13-7
SSPOL bit, 13-6
SSTATUS field, 13-10
State machine status field, see SSTATUS field
STEP VALUE field
NIPR1 register, 14-18
NIPR2 register, 14-28
STOP bit
USTCNT1 register, 14-11
USTCNT2 register, 14-20
Stop bit transmission bit, see STOP bit
Suggested reading, xxix
Supervisor-use-only protected memory block bit, see
SOP bit
SYSCLK SEL field, 4-8
System clock select field, see SYSCLK SEL field
System control register, see SCR register
System integration module, 5-1
T
Tap selection field, see SELECT field
TCMP1 register, 12-9
TCMP2 register, 12-9
TCN1 register, 12-11
TCN2 register, 12-11
TCR1 register, 12-11
TCR2 register, 12-10
TCTL1 register, 12-6
TCTL2 register, 12-6 to 12-7
TE bit, 13-9
TEEN bit, 13-9
TEN bit, 12-7
TF bit, 13-9
TFEN bit, 13-8
TH bit, 13-9
THEN bit, 13-8
Timer 1 interrupt pending bit, see TMR1 bit
Timer 1 interrupt status bit, see TMR1 bit
Timer 2 interrupt pending bit, see TMR2 bit
Timer 2 interrupt status bit, see TMR2 bit
Timer capture register 1, see TCR1 register
Timer capture register 2, see TCR2 register
Timer capture registers, overview
CAP field transition selection, 12-3
CAPT status bit, setting, 12-3
TIN input, switching, 12-3
Timer compare register 1, see TCMP1 register
Timer compare register 2, see TCMP2 register
Timer control register 1, see TCTL1 register
Timer control register 2, see TCTL2 register
Timer counter register 1, see TCN1 register
Timer counter register 2, see TCN2 register
Timer counter value field, see COUNT field
Timer enable bit, see TEN bit
Timer for real-time clock bit, see MRTI bit
Timer prescaler register 1, see TPRER1 register
Timer prescaler register 2, see TPRER2 register
Timer signals
introduction, 2-8
timer 1 input, see TOUT/TIN/PB6 pin
timer 1 output, see TOUT/TIN/PB6 pin