Motorola MC68VZ328 - Manual (Page 125)

Programming Model
DRAM Controller 7-15
LSP
Bit 4 Light Sleep—Setting this bit enables the core or
LCD controller to access the DRAM when the RM
bit is set (DRAM is in self-refresh mode).
Self-refresh mode is temporarily interrupted for
the DRAM access and automatically returns to
self-refresh mode once the transfer is complete.
Transfers in this mode are much slower than nor-
mal. Therefore, it is best to clear the RM bit if the
DRAM is to be awake for extended periods of
time. If this bit is clear, DRAM accesses will not
occur when RM is set, and attempts will cause
the bus to time out. 0 = Self-refresh is interrupted only by clearing the
RM bit.
1 = Self-refresh is temporarily interrupted by core
or LCD controller accesses to DRAM.
SLW
Bit 3 Slow RAM—Setting this bit extends the RAS
precharge period for slower DRAM devices. This
bit should be set if the RAS precharge time
requirement for the device being used is greater
than 60 ns (33 MHz system clock) or 120 ns
(16.58 MHz system clock). 0 = Normal RAS precharge (2 system clocks).
1 = Extended RAS precharge for slower DRAM
devices (4 system clocks).
LPR
Bit 2 Low-Power Refresh Enable—This bit is used to
control the refresh during low-power modes. 0 = Disable low-power refresh mode.
1 = Enable low-power refresh mode.
RST
Bit 1 Reset Burst Refresh Enable—This bit controls
the refresh type during RESET assertion. 0 = Normal distributed refresh operation during
DRAM reset function.
1 = Continuous burst refresh operation during
DRAM reset function.
DWE
Bit 0 DRAM Write-Enable—This bit is used to enable
the DWE signal, which can be employed when a
DRAM is being used that needs an independent
write-enable signal, rather than sharing one with
the UWE signal. 0 = Disable DWE.
1 = Enable DWE.
1.The first Fast Page Mode access will always be 4 clocks. When an LCD controller cycle and a refresh request
collide before the LCD controller cycle starts, refresh will go first, and N more clocks will be added to the first
access (N is the number of system clock cycles required for refresh)
.
Table 7-7. DRAM Control Register Description (Continued)
Name Description Setting