Motorola MC68VZ328 - Manual (Page 84)

5-2 MC68VZ328 User’s Manual
Programming Model
5.2 Programming Model
The following sections provide detailed programming information about the system control register and
the other registers associated with its operation.
5.2.1 System Control Register
The 8-bit read/write system control register (SCR) resides at the address 0xFFFFF000 or 0xXXFFF000
(where XX is “don’t care”) after reset. The SCR and all other internal registers cannot be accessed in the
68000’s user mode if the SO bit is set to 1. The bit assignments for the register are shown in the following
register display. The settings for the bits in the register are listed in Table 5-1.
SCR System Control Register 0x(FF)FFF000
BIT 7 6 5 4 3 2 1 BIT 0
BETO WPV PRV BETEN SO DMAP WDTH8
TYPE rw rw rw rw rw rw rw
RESET
0 0 0 1 1 1 0 0
0x1C
Table 5-1. System Control Register Description
Name Description Setting
BETO
Bit 7 Bus Error Time Out—This status bit indicates
whether or not a bus-error-timer time out has
occurred. When a bus cycle is not terminated by
the DTACK signal after 128 clock cycles have
elapsed, the BETO bit is set. However, the
BETEN bit must be set for a bus error time out to
occur. This bit is cleared by writing a 1 (writing a
0 has no effect). 0 = A bus-error-timer time out did not occur.
1 = A bus-error-timer time out has occurred
because an undecoded address space has
been accessed or because a write-protect or
privilege violation has occurred.
WPV
Bit 6 Write-Protect Violation—This status bit indi-
cates that a write-protect violation has occurred.
If a write-protect violation occurs and the BETEN
bit is not set, the current bus cycle will not termi-
nate. The BETEN bit must be set for a bus error
exception to occur during a write-protect viola-
tion. This bit is cleared by writing a 1 (writing a 0
has no effect). 0 = A write-protect violation did not occur.
1 = A write-protect violation has occurred.
PRV
Bit 5 Privilege Violation—This status bit indicates
that if a privilege violation occurs and the BETEN
bit is not set, the cycle will not terminate. The
BETEN bit must be set for a bus error exception
to occur during a privilege violation. This bit is
cleared by writing a 1 (writing a 0 has no effect). 0 = A privilege violation did not occur.
1 = A privilege violation has occurred.
BETEN
Bit 4 Bus Error Time-Out Enable—This control bit
enables the bus error timer. 0 = Disable the bus error timer.
1 = Enable the bus error timer.
SO
Bit 3 Supervisor Only—This control bit limits on-chip
registers to supervisor accesses only. 0 = User and supervisor mode.
1 = Supervisor-only mode.