Motorola MC68VZ328 - Manual (Page 48)

2-6 MC68VZ328 User’s Manual
Interrupt Controller Signals
2.6 Bus Control Signals
The bus control signals are used for both the configuration and operation of the MC68VZ328 bus. The
following descriptions provide detailed information about programming the signals and their use.
• LWE/LB, UWE/UB—Lower Byte Write-Enable and Upper Byte Write-Enable, or Lower Byte and
Upper Byte data strobes. For all chip-select cycles except CSB[1:0], these two pins are LWE and
UWE. They are used as lower and upper write-enable signals to a 16-bit port. If the chip-select is
set to 8-bit port (the BSW bit is clear), use only the UWE signal for write-enable control. UWE can
be used as a DRAM write-enable if DRAM refresh does not require that UWE stay high. Otherwise,
DWE should be used. For CSB[1:0] cycles, if the SR16 bit is clear in the CSCTRL1 register, these
two pins are LWE and UWE and function as previously described. If the SR16 bit is set, these two
pins are UB and LB. These two data strobe signals are normally used to connect to UDS and LDS
of the 16-bit memory chip.
• DWE/UCLK/PE3—DRAM Write-Enable, UART Clock, or Port E bit 3. Use the DWE signal with
DRAM, which requires an independent write-enable signal rather than one that is shared with
UWE. This signal stays high during refresh cycles. This pin defaults to a PE3 input signal. To select
the DWE function, program Port E to DWE and enable the DWE signal by writing a 1 to the DWE
bit of the DRAMC register, which is described in Section 7.3.2, “DRAM Control Register,” on
page 7-14. If this bit is not enabled, the UCLK signal function is selected, which is an input clock
to the UART module. For a description of the UCLK signal, refer to Section 14.2.3, “Serial
Interface Signals,” on page 14-3. This pin defaults to GPIO input pulled high.
• BUSW/DTACK/PG0—Bus Width, Data Transfer Acknowledge, or Port G bit 0. BUSW is the
default bus width for the CSA0 signal. The DTACK signal is the external input data acknowledge
signal. The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the
RESET signal. Its mode will determine the default bus width for CSA0. For example, a logic low
of BUSW on reset means that CSA0 connects to an 8-bit memory device, and a logic high of BUSW
on reset means that CSA0 connects to a 16-bit memory device. After reset, this pin defaults to the
DTACK input signal. DTACK can be configured as output by programming the Port G DIR register.
If it is input, only those chip-select cycles using external DTACK will be affected. Chip-select
cycles of internal DTACK will ignore the input status. This pin can be configured to GPIO after
system reset. For a 16-bit CSA0-selected memory device, it is recommended that this signal be
pulled up, externally.
• OE—Output Enable. This active low signal is asserted during a read cycle of the MC68VZ328
microprocessor, which enables the output of either ROM or SRAM.
• UDS/PK3, LDS/PK2—Data strobes or GPIO. UDS and LDS are 68000 CPU data strobe signals.
These pins default to GPIO input pulled high.
• RW/PK1—Read/Write or Port K bit 1. RW is the 68000 CPU read/write signal. This pin defaults to
GPIO input pulled high.
2.7 Interrupt Controller Signals
This section describes signals that are used by the MC68VZ328 interrupt controller.
• INT[3:0], IRQ[3:1], IRQ6/PD[7:0]—Interrupt bits 3–0, Interrupt Request bits 3-1, or Port D bits
7–0. INT[3:0], IRQ[3:1], and IRQ6 can be configured as edge or level trigger interrupt signals. To
support keyboard applications, the I/O function can be used with interrupt capabilities, which are
described in Chapter 9, “Interrupt Controller.” These pins default to GPIO input pulled high.