Motorola MC68VZ328 - Manual (Page 89)

Chip-Select Logic 6-1
Chapter 6
Chip-Select Logic
This chapter describes the chip-select logic’s function and operation and provides programming
information for controlling its operation.
6.1 Overview of the CSL
The MC68VZ328 microprocessor contains eight general-purpose, programmable chip-select signals,
which are used to select external devices on the address and data bus. The signals are arranged in four
groups of two—CSA[1:0], CSB[1:0], CSC[1:0], and CSD[1:0].
CSA0 is a special-purpose chip-select signal, which is the boot device chip-select. After reset, in normal
mode all the addresses are mapped to CSA0 until such time that the group base address A is programmed
and the chip-select enable (EN) bit is set in the appropriate chip-select register. From that point forward,
CSA0 does not decode globally and is only asserted when decoded from the programming information in
the chip-select register.
Group C (CSC0/CSC1) and Group D (CSD0/CSD1) chip-selects are unique in that they can also be
programmed as row address strobe (RAS0/RAS1) and column address strobe (CAS0/CAS1) for the
DRAM interface. For details, refer to Section 7.3.2, “DRAM Control Register,” on page 7-14 and
Section 6.3.3, “Chip-Select Registers,” in this chapter.
Each memory area can be defined as an internally generated cycle-termination signal, called DTACK, with
a programmable number of wait states. This feature saves
board space that would otherwise be used for
cycle-termination logic. Using CDL, the system designer can adopt a flexible memory configuration based
on cost and availability. Up to four different classes of devices and memory can be used in a system
without the need for external decode or wait-state generation logic. Specifically, 8- or 16-bit combinations
of ROM, SRAM, flash memory and DRAM (EDO RAM, Fast Page Mode, or synchronous) are supported,
as shown in Table 6-1 on page 6-2.