Motorola MC68VZ328 - Manual (Page 197)

Programming Model
I/O Ports 10-27
10.4.7.4 Port F Pull-up/Pull-down Enable Register
The Port F pull-up/pull-down enable register (PFPUEN) controls the pull-up resistors for each line in Port
F. The settings for the PFPUEN bit positions are shown in Table 10-34.
PFPUEN Port F Pull-up/Pull-down Enable Register 0x(FF)FFF42A
10.4.7.5 Port F Select Register
The Port F select register (PFSEL) determines if a bit position in the data register (PFDATA) is assigned as
a GPIO or to a dedicated I/O function. The settings for the PFSEL bit positions are shown in Table 10-35.
PFSEL Port F Select Register 0x(FF)FFF42B
BIT 7 6 5 4 3 2 1 BIT 0
PU7 PD6 PD5 PD4 PD3 PU2 PU1 PU0
TYPE rw rw rw rw rw rw rw rw
RESET
1 1 1 1 1 1 1 1
0xFF
Table 10-34. Port F Pull-up/Pull-down Enable Register Description
Name Description Setting
PU7
Bit 7 Pull-up—This bit enables the pull-up
resistor on the port. 0 = Pull-up resistor is disabled
1 = Pull-up resistor is enabled
PDx
Bits 6–3 Pull-down—These bits enable the
pull-down resistors on the port. 0 = Pull-down resistors are disabled
1 = Pull-down resistors are enabled
PUx
Bits 2–0 Pull-up—These bits enable the pull-up
resistors on the port. 0 = Pull-up resistors are disabled
1 = Pull-up resistors are enabled
BIT 7 6 5 4 3 2 1 BIT 0
SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0
TYPE rw rw rw rw rw rw rw rw
RESET
1 0 0 0 0 1 1 1
0x87
Table 10-35. Port F Select Register Description
Name Description Setting
SELx
Bits 7–0 Select—These bits select whether the internal chip
function or I/O port signals are connected to the pins. 0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.