Motorola MC68VZ328 - Manual (Page 315)

Application Guide 18-1
Chapter 18
Application Guide
This chapter contains helpful information that will assist with integrating the MC68VZ328 into new or
existing designs. It includes a design checklist and instructions for using the MC68VZ328 Application
Development System (ADS) board to get the design process started as quickly as possible.
18.1 Design Checklist
When the MC68VZ328 microprocessor is being integrated into an application, the following items can be
used as guides during the design process. These guidelines are the result of issues that frequently occurred
during debugging or in the process of operating actual designs.
18.1.1 Determining the Chip ID and Version
Each chip has different sets of numbers etched onto it, and one of these sets is the mask and revision
number for that particular chip. The mask number and the revision number are combined into one. For
example, with the number 0F98S, 0 is the revision number and F98S is the mask number. This information
is necessary for obtaining the correct errata information for that version of the chip, ensuring more efficient
product design. Once the mask and revision numbers are known, go to the DragonBall Web site
(http://www.Motorola.com/DragonBall) and look for any MC68VZ328 chip errata pertaining to those
numbers. If Web access is not available, contact the local Motorola sales office.
18.1.2 8-Bit Bus Width Issues
To ensure maximum flexibility, the MC68VZ328 supports both 8- and 16-bit data bus modes. Except the
chip-select group A, which carries the boot chip select signal CSA0 and is normally connected to boot
ROM, all the chip select signals are programmable to 8-bit or 16-bit mode after reset. The data bus width
for the CSA0 and CSA1 signals is only controlled by the BUSW/DTACK/PG0 signal. For a system with
16-bit data boot ROM, BUSW is pulled high or left unconnected during system reset. For an 8-bit data
boot ROM system, BUSW must be externally driven low during system reset. The BUSW status is latched
by the rising edge of the RESET signal, and the latched BUSW status is indicated by the BSW bit of the
chip-select A control register. See Section 6.3.3, “Chip-Select Registers,” on page 6-8 for more details.
Also, after reset, the BUSW/DTACK/PG0 pin can be selected as a DTACK or PG0 function, but it defaults
to the DTACK function. This signal should be permanently driven low for an 8-bit system to force all bus
cycles to a zero wait state until this pin is reconfigured to the PG0 function. Fortunately, the system clock
is divided by two (the PRESC bit in the PLLCR register is set) after reset, which doubles the length of each
bus cycle and provides ample access time to memories. Therefore, BUSW/DTACK/PG0 should be
programmed to the PG0 function before the system clock is configured to divide by one (the PRESC bit in
the PLLCR register is cleared).