Table 16-2, Ice module control compare register description -6, Table 16-3 – Motorola MC68VZ328 User Manual
Page 298: Ice control mask register description -6
16-6
MC68VZ328 User’s Manual
Programming Model
16.2.2
In-Circuit Emulation Module Control Compare and
Mask Register
The in-circuit emulation module control compare (ICEMCCR) register is used to set the breakpoint at a
specific bus cycle, and the in-circuit emulation module control mask register (ICEMCMR) is used to mask
the corresponding control bit in the ICEMCMR. In bus breakpoint mode, the control signal comparator
will compare the predefined control signals with the address compare match signal to generate the
EMUBRK signal in single breakpoint mode. In multiple breakpoint mode, EMUBRK is an input signal
and will AND with the result from the address comparator and control comparator to generate the internal
match signal. For program break mode, these two registers are “don’t care.” The register bit assignments
for both the compare and mask registers are shown in the following register displays. The settings for the
bits are described in Table 16-2 and Table 16-3.
ICEMCCR
ICE Module Control Compare Register
0x(FF)FFFFFD08
ICEMCMR
ICE Control Mask Register
0x(FF)FFFFFD0A
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
RW
PD
TYPE
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 16-2. ICE Module Control Compare Register Description
Name
Description
Setting
Reserved
Bits 15–2
Reserved
These bits are reserved and
should be set to 0.
RW
Bit 1
Read or Write Cycle Selection—This bit is used to select the
break at a read cycle or write cycle. When a break at a read cycle
is selected, a breakpoint at the ROM location is possible.
0 = Write cycle breakpoint.
1 = Read cycle breakpoint.
PD
Bit 0
Program or Data Cycle Selection—This bit is used to select the
break at a program cycle or data cycle.
0 = Data bus cycle.
1 = Instruction bus cycle.
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
RWM
PDM
TYPE
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 16-3. ICE Control Mask Register Description
Name
Description
Setting
Reserved
Bits 15–2
Reserved
These bits are reserved and should be set to 0.