Motorola MC68VZ328 - Manual (Page 249)

SPI 2 Operation
Serial Peripheral Interface 1 and 2 13-13
13.5.1 SPI 2 Phase and Polarity Configurations
The SPI 2 module uses the SPICLK2 signal to transfer data in and out of the shift register. Data is clocked
using any one of four programmable clock phase and polarity variations. In phase 0 operation, output data
changes on the falling clock edges and input data is shifted in on rising edges. The most significant bit is
output when the CPU loads the transmitted data. In phase 1 operation, output data changes on the rising
edges of the clock and is shifted in on falling edges. The most significant bit is output on the first rising
SPICLK2 edge. Polarity inverts SPICLK2, but does not change the edge-triggered events that are internal
to the SPI 2 module. This flexibility allows it to operate with most serial peripheral devices on the market.
13.5.2 SPI 2 Signals
The following signals are used to control the SPI 2 module:
• SPITXD—The Transmit Data pin, which is multiplexed with PE0, is the output of the shift register.
A new data bit is presented, but it depends on whether you have selected phase or polarity.
• SPIRXD—The Receive Data pin, which is multiplexed with PE1, is the input to the shift register.
A new bit is shifted in, but it depends on whether you have selected phase or polarity.
• SPICLK2—The SPI 2 master Clock output pin is multiplexed with PE2. When the SPI 2 module is
triggered, the selected number of clock pulses are issued. In polarity 0 mode, this signal is low while
the SPI 2 module is idle, and it is high in polarity 1 mode.
NOTE:
A chip-select signal may be required by the external device. A GPIO pin
may be assigned to this function.