Sdram power-down register = 1) -25 – Motorola MC68VZ328 User Manual
Page 341
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AC Electrical Characteristics
Electrical Characteristics
19-25
19.3.20
Page-Hit CPU Read Cycle in Power-down Mode (CAS
Latency = 1, Bit APEN of SDRAM Power-down
Register = 1)
Figure 19-21 shows the timing diagram for the page-hit CPU read cycle in power-down mode. The signal
values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information
about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7,
“DRAM Controller.”
Figure 19-21. Page-Hit CPU Read Cycle in Power-down Mode Timing Diagram
S0
S2
S4
S4
S4
S4
S4
S4
S3
S1
SDCLK
RAS
SCKEN
D[15:0]
CAS
A[16:1]/MD[15:0]
SDA10
CS
WE
DQM
DTACK
Read
Command
S4
S5
S6
S7
Col
7
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